{
"attributes": null,
"course": {
"begin": "F2023",
"courseIdentifierParentId": 356505,
"courseNumber": "M16",
"courseTitle": "Logic Design of Digital Systems",
"department": "Electrical Engineering",
"departmentParentId": 4521,
"end": "",
"maxUnits": 4.0,
"minUnits": 4.0,
"pathways": [],
"prefix": "EC ENGR",
"prefixDescription": "Electrical Engineering",
"prefixParentId": 13409
},
"courseAttributes": null,
"receivingAttributes": null,
"sendingArticulation": null,
"templateOverrides": null,
"type": "Course",
"visibleCrossListedCourses": [
{
"begin": "F2023",
"courseIdentifierParentId": 295362,
"courseNumber": "M51A",
"courseTitle": "Logic Design of Digital Systems",
"department": "Computer Science",
"departmentParentId": 3200,
"end": "",
"maxUnits": 4.0,
"minUnits": 4.0,
"pathways": [],
"prefix": "COM SCI",
"prefixDescription": "Computer Science",
"prefixParentId": 551
}
]
}